module branch(
  input i_ex1_branch,
  input [31:2] i_ex1_branch_dest,
  input i_wb_branch,
  input [31:2] i_wb_branch_dest,
  output o_branch,
  output reg [31:2] o_branch_dest
);

assign o_branch = i_ex1_branch | i_wb_branch;

always @* begin
  case (1'b1)
    i_ex1_branch: o_branch_dest = i_ex1_branch_dest;
    i_wb_branch: o_branch_dest = i_wb_branch_dest;
  endcase
end

endmodule
